1. Field of the Invention
The present invention is directed in general to data communications. In one aspect, the present invention relates to a method and system for generating timer request signals for multiple channels in a multiprocessor computer device.
2. Related Art
As is known, communication technologies that link electronic devices may use multiprocessor switching devices to route and process signal information. Some communication technologies interface a one or more processor devices for processing packet-based signals in a network of computer systems. Generally, packets are used to communicate among networked computer and electronic systems. Thus, each networked system must receive and transmit packets, and must process the packets directed to that system to determine what is being transmitted to that system.
Typically, each computer system includes one or more interfaces or ports on which packets are transmitted and received. Additionally, each interface generally includes a dedicated DMA engine used to transmit received packets to memory in the system and to read packets from the memory for transmission. If a given system includes two or more packet interfaces, the system includes DMA engines for each interface. Where a computer system processes multiple packet channels using the DMA engines, the processor(s) in the system must be able to monitor the status of the DMA transfers for each channel and other system-related functions associated with the channel transfers.
Conventional systems have used timing circuits to generate timing signals that are used in connection with the status monitoring functions and system operations. Such timing circuits typically are constructed with a counter that counts up or down, and when the counter reaches zero (for count down counters) or a preset value, a timer request is generated. When multiple counter-based timers are used for monitoring the status of multiple independent channels, the conventional timing circuit approach requires multiple counters that use significant chip area to provide a timer functionality for each channel. As the number of channels increases, the unwieldiness of conventional approaches also increases.
Therefore, a need exists for methods and/or apparatuses for quickly and efficiently generating timer request signals for multiple channels so that each timer request may be independently programmable to have its own time-out setting. Further limitations and disadvantages of conventional systems will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.